The present invention relates to clock distributing logic for reducing clock skew during the distribution of a clock signal in a circuit. More particularly, the present invention relates to a clock skew control design method for designing clock distributing logic in a manner to reduce clock skew in a circuit by varying the driving ability of last-stage clock amplifying gates included in the clock distributing logic.
Generally, the increase of clock skew in an LSI circuit or a microprocessor increases data transfer time (path delay) necessary to transfer data from a flip-flop on the side of a source to a flip-flop on the side of a sink in the LSI circuit or microprocessor.
Such a path delay is expressed by the following expression. EQU Tc=TgateD+TwireD+Tskew (1)
where Tc is a time necessary for data to be transferred from the flip-flop on side of the source to the flip-flop on the side of the sink, i.e., path delay, TgateD is a time necessary for data to pass a logic gate disposed between the flip-flop on the side of the source and the flip-flop on the side of the sink, i.e., gate delay, TwireD is a capacitive and resistive delay caused by a wiring line connecting the flip-flop on the side of the source through the logic gate to the flip-flop on the side of the sink, i.e., wire delay, and Tskew is clock skew.
Generally, the path delay Tc is equal to the operating frequency (machine cycle) of the LSI circuit or the microprocessor. Accordingly, the reduction of the path delay is an important problem in decreasing the length of the machine cycle. High-speed devices have been employed to reduce gate delay and low-resistance, low-capacitance wiring lines have been employed to reduce wiring delay.
However, the ratio of clock skew relative to the other causes of delay has increased as the length of the machine cycle has decreased by the employment of high-speed gates and high-speed wiring lines. In fact, the ratio of clock skew to the other causes of delay is nearly equal to 10% of the total delay. Therefore, the reduction of clock skew is one of the most important problems in enhancing machine cycle.
A generally known clock skew reducing method provides circuits, respectively connecting flip-flops to the clock input pin of a LSI circuit or microprocessor, with the same number of clock amplifying gates and respectively connects the flip-flops by using wiring lines having the same length to the clock input pin. Such connections using wiring lines having the same length cause the time necessary for transferring a clock signal from the clock input pin through the circuits to the flip-flops to coincide with a reference time. This method is not very effective with small scale circuits.
Another generally known clock skew reducing method calculates delays in transferring a clock signal from the clock input pin to the flip-flops and adjusts the lengths of wiring lines connecting the last clock amplifying gates to the corresponding flip-flops according to the amount of the delay necessary for transferring a clock signal from the clock input pin through the circuit to the flip-flops deviates from a reference time. According to this method adjusting the lengths of wiring lines effects wire delay (capacitive delay) in the circuit. Thus, the flip-flops are driven at the same time. This method, described in "Exact Zero Skew", IEEE International Conference on Computer-aided Design 1991, November 11-14, increases costs and requires extra processing steps to form the circuits.
The above-described clock skew reducing methods also suffer from disadvantages other than those described above. For example, the above-described clock skew reducing methods unnecessarily increase the number of clock wiring lines and require a relatively large number of clock amplifying gates. Further there are diminishing returns for using the above described clock skew reducing methods as the density of logic gates increase and as the performance of microprocessors and LSI circuits increase. Recently developed techniques for designing and fabricating semiconductor circuits and delay simulation have reduced clock skew remarkably.
However, significant fortification of LSI circuits and microprocessors with clock logic circuits, clock distributing amplifying gates and clock wiring lines included particularly in microprocessors to suppress clock skew has brought about problems including an increase in the quantity of hardware and an increase in the power consumption of such LSI circuits and microprocessors. These problems are significant even though such fortification of LSI circuits and microprocessors reduce clock skew nearly to null.